The present invention relates to a differential charge pump, in particular for use in a tuning system including a phase-locked loop, for generating currents, comprising a first input and an inverse second input, in particular for receiving differential signals from a phase comparator, first current source means for generating a first current in accordance with the signal inputted into said first input, second current source means for generating an inverse second current in accordance with the signal inputted into said second input, and a first output and a second output for outputting said first and second currents, respectively.
A differential charge pump is used e.g. in tuning systems including a phase-locked loop (PLL) with large tuning range (xe2x80x9cSonetxe2x80x9d/xe2x80x9cSDHxe2x80x9d applications) wherein a preferable application is the Data and Clock Recovery (DCR) function. However, such a differential charge pump can be used in any type of tuning system mostly in relationship with a linear phase detector so that the above mentioned implementation does not impair the generality of the application of such a differential charge pump.
In a PLL environment, a phase detector (PD) drives differentially the input of the differential charge pump. It can be of linear type or bang-bang type since the charge pump has to work in a linear mode. When using bang-bang phase detectors, the input pulses are rectangular signals and are linearly amplified by the differential charge pump.
EP 0 718 978 A1 discloses a differential charge pump comprising a lowpass filter network, two identical current generators for injecting the same current in a substantial continuous manner on two significant nodes of the lowpass filter and two pairs of identical, switchingly controlled current generators connected to said nodes, respectively, each capable of pulling a current. The two generators forming each of said two pairs are controlled by one of a pair of control signals and by the inverted signal of the other of said pair of control signals, respectively. All four switchingly controlled generators may be of the same type. The two current generators employed for continuously injecting the same current on the two nodes of the lowpass filter are controlled through a common feedback loop. The low pass filter network is chargeable and dischargeable by means of the switchingly controlled current generators.
From U.S. Pat. No. 6,111,470 A known is a PLL circuit with charge pump noise cancellation, wherein the switching time of the PLL circuit can be reduced by increasing circuit bandwidth. A charge pump is commonly used in the PLL circuit to drive a voltage control oscillator (VCO). The increase in bandwidth intensifies the noise which is contributed by the charge pump. To reduce such charge pump noise, a chopper stabilizer circuit modulates the noise to a sufficiently high frequency so that a low-pass filter filters out the modulated noise.
U.S. Pat. No. 5,485,125 discloses a phase-locked variable frequency oscillator arrangement including a voltage controlled oscillator (VCO) which is controlled by a control signal produced by charging or discharging of a capacitor in a charge pump circuit. The charge pump circuit includes current sources driven by up or down command signals from a phase detector which detects the phase of the VCO output. When the command signals are simultaneously active, a logic gate circuit supplies a reset pulse to the phase detector via a delay device which is adapted to the rise time of the current in the current sources. The delay device includes a transistor which forms a switched pair with one of the transistors forming the current sources. The reset signal is produced when the current of such transistor reaches a selected fraction of its normal current, after being turned on by the logic gate circuit.
Further PLL circuits including a charge pump in a similar manner as described above are disclosed in U.S. Pat. Nos. 5,534,823 A, 5,943,382 A and 5,113,152 A.
As already mentioned above, a differential charge pump can be preferably used in highspeed tuning systems where speed plays an important role, since the differential implementation allows large swings.
However, a problem is the occurrence of common mode noise and noise coming from the substrate and the power supply.
An objection of the present invention is to provide a differential charge pump which is robust towards common mode noise and noise coming from the substrate and power supply.
In order to achieve the above and other objects, according to the present invention, there is provided a differential charge pump, in particular for use in a tuning system including a phase-locked loop, for generating currents, comprising
a first input and an inverse second input, in particular for receiving differential signals from a phase comparator,
first current source means for generating a first current in accordance with the signal inputted into said first input,
second current source means for generating an inverse second current in accordance with the signal inputted into said second input; and
a first output and a second output for outputting said first and second currents, respectively, characterized by
a first controllable common mode current source means for additionally feeding common mode current to said second output,
a second controllable common mode current source means for additionally feeding common mode current to said second output; and
common mode controlling means for controlling said first and second common mode current source means so as to make the common mode currents essentially equal to the currents generated by said first and second current source means, respectively.
The differential charge pump having a construction in accordance with the present invention is robust towards common mode noise and noise coming from the substrate and power supply, wherein the common mode circuit has low noise properties due to reduction of 1/f noise. In particular, the differential charge pump according to the present invention can be advantageously for burst data applications since offset compensation can be achieved. In case of an implementation in a PLL arrangement, the invention allows double swing at the output with the effect of reducing the gain constant of the VCO which again helps in reducing the residual phase noise of the PLL.
Further advantageous embodiments of the present invention are defined in the dependent claims.
In a preferred embodiment of the present invention, the common mode controlling means controls said first and second controllable common mode current source means under the condition that the common mode voltage at said first and second outputs is made essentially half of said supply voltage. This embodiment comprises a preferred construction for allowing double swing at the output.
For the above preferred embodiment it is advantageous to provide first common mode voltage detecting means for detecting the output common mode voltage at said first and second outputs, wherein the signals outputted from said first common mode voltage detecting means and representing the common mode voltages at the outputs are inputted into said common mode controlling means.
In accordance with a further preferred embodiment of the present invention, the common mode controlling means controls said first and second controllable common mode current source means under the condition that the common mode voltage at said first and second outputs is made essentially equal to the common mode voltage at said first and second inputs. Such condition is very advantageous to realize a situation in order to make the common mode current generated by said first and second controllable common mode current source means equal to the currents generated by said first and second current source means, respectively.
For the above recently mentioned embodiment it is advantageous to provide, in additional to the above mentioned first common mode voltage detecting means, second common mode voltage detecting means for detecting the input common mode voltage at said first and second inputs, wherein the signals outputted from said second common mode voltage detecting means and representing the common mode voltages at the inputs are inputted into said common mode controlling means, too.
The above recently mentioned embodiment can further comprise a differential current amplifier means including at least a first transistor with its base connected to a path leading to said first input and its emitter-collector path defining a path leading to said first output, and a second transistor with its base connected to a path leading to said second input and its emitter-collector path defining a path leading to said second output, wherein the common mode controlling means controls said first and second controllable common mode current source means so as to make the common mode currents essentially equal to the currents flowing through the emitter-collector paths of said first and second transistors, respectively. Further or alternatively, the common mode voltage at the emitter or collector of said first and second transistors is essentially equal to the common mode voltage at the base of said first and second transistors.
A still further preferred embodiment is characterized by a dynamic element matching means coupling said first and second controllable common mode current source means with said first and second outputs, respectively, for making the common mode currents generated by said first and second common mode current sources essentially equal to each other, said dynamic element matching means comprising a first input connected to said first controllable common mode current source means, a second input connected to said second controllable common mode current source means, a first output connected to a path leading to said first output and a second output connected to a path leading to said second output. The provision of such a dynamic element matching means helps in a very convenient way to minimize the 1/f noise and offset. A further advantage of this embodiment is that the dynamic element matching means is not provided in the signal path such that it does not affect the signal.
Moreover, an output filter means can be provided where the currents are integrated, respectively.
When combining both the above recently mentioned embodiments, provided can be a first cascode transistor with its base applied to a bias voltage and its emitter-collector path coupling the first output of said dynamic element matching means to said first output, and a second cascode transistor with its base applied to a bias voltage and its emitter-collector path coupling the second output of said dynamic element matching means to said second output, said first and second cascode transistors isolating said output filter means from said dynamic element matching means. The use of such cascode transistors facilitates local (in particular low-pass) filtering of spurious signals with extra attenuation due to the output filter means.
Usually, the bias voltage applied to the base of said first cascode transistor is equal to the bias voltage applied to the base of said second cascode transistor. Preferably, said first and second cascode transistors, are MOS transistors in particular PMOS transistors.
In order to provide high impedance and less loading effects with parasitics, output buffer means can be provided preferably coupled between the output filter means and the outputs.